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general description the max1286?ax1289 are low-cost, micropower, seri-al output 12-bit analog-to-digital converters (adcs) available in a tiny 8-pin sot23 and an 8-pin tdfn. the max1286/max1288 operate with a single +5v supply. the max1287/max1289 operate with a single +3v sup- ply. the devices feature a successive-approximation adc, automatic shutdown, fast wakeup (1.4?), and a high-speed 3-wire interface. power consumption is only 0.5mw (v dd = +2.7v) at the maximum sampling rate of 150ksps. autoshutdown (0.2?) between conversionsresults in reduced power consumption at slower throughput rates. the max1286/max1287 provide 2-channel, single-ended operations and accept input signals from 0 to v ref . the max1288/max1289 accept true-differential inputs ranging from 0 to v ref . data is accessed using an external clock through the 3-wirespi-/qspi-/microwire-compatible serial inter- face. excellent dynamic performance, low power, ease of use, and small package size make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low power consumption and minimal space. applications low-power data acquisitionportable temperature monitors flowmeters touch screens features ? single-supply operation +3v (max1287/max1289)+5v (max1286/max1288) ? autoshutdown between conversions ? low power 245 a at 150ksps 150 a at 100ksps 15 a at 10ksps 2 a at 1ksps 0.2 a in shutdown ? true-differential track/hold, 150khz sampling rate ? software-configurable unipolar/bipolarconversion (max1288/max1289 only) ? spi-/qspi-/microwire-compatible interface fordsps and processors ? internal conversion clock ? 8-pin sot23 and 8-pin tdfn packages max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs ________________________________________________________________ maxim integrated products 1 cnvst ref gnd 12 8 7 sclk dout ain1 (ain+) ain2 (ain-) v dd sot23 top view ( ) are for the max1288/max1289 3 4 6 5 max1286 max1289 cnvst gnd 6 7 8 dout sclk ref 5 4 2 1 ain1 (ain+) v dd tdfn max1286 max1289 3 ain2 (ain-) ep + pin configurations 19-2231; rev 3; 8/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information autoshutdown is a trademark of maxim integrated products, inc. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. part pin-package top mark max1286 eka-t 8 sot23 aafa max1286eta+t 8 tdfn-ep* +afr max1287 eka-t 8 sot23 aaew max1287eta+t 8 tdfn-ep* +afn max1288 eka-t 8 sot23 aafc max1288eta+t 8 tdfn-ep* +aft max1289 eka-t 8 sot23 aaey max1289eta+t 8 tdfn-ep* +afp note: all devices specified over the -40? to +85? operating range . + denotes a lead(pb)-free/rohs-compliant package . - denotes a package containing lead(pb). * ep = exposed pad. evaluation kit available downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v dd = +2.7v to +3.6v, v ref = +2.5v for max1287/max1289, or v dd = +4.75v to +5.25v, v ref = +4.096v for max1286/max1288, 0.1? capacitor at ref, f sclk = 8mhz (50% duty cycle), ain- = gnd for max1288/max1289. t a = t min to t max, unless otherwise noted. typical values at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v cnvst, sclk, dout to gnd....................-0.3v to (v dd + 0.3v) ref, ain1 (ain+), ain2 (ain-) to gnd......-0.3v to (v dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 8-pin sot23 (derate 9.70mw/? above t a = +70?) ...696mw 8-pin tdfn (derate 18.5mw/? above t a = +70?) ...1481mw operating temperature range ...........................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) lead(pb)-free packages...............................................+260? packages containing lead(pb).....................................+240? parameter symbol conditions min typ max units dc accuracy (note 1) resolution 12 bits relative accuracy (note 2) inl 1.0 lsb differential nonlinearity dnl no missing codes over temperature 1.0 lsb offset error 2 4 lsb gain error (note 3) 2 4 lsb gain temperature coefficient 0.4 ppm/ c offset tem p er atur e c oeffi ci ent 0.4 p p m/ c channel-to-channel offset matching 0.1 lsb channel-to-channel gain matching 0.1 lsb input common-mode rejection cmr v cm = 0v to v dd ; zero scale input 0.1 mv dynamic specifications: (f in (sine-wave) = 10khz, v in = 4.096vp-p for max1286/max1288 or v in = 2.5v p - p for max1287/max1289, 150ksps, f sclk = 8mhz, (50% duty cycle) ain- = gnd for max1288/max1289) signal to noise plus distortion sinad 70 db total harmonic distortion(up to the 5 th harmonic) thd -82 db spurious-free dynamic range sfdr 86 db full-power bandwidth -3db point 1 mhz full-linear bandwidth sinad > 68db 100 khz conversion rate conversion time t conv does not include t acq 3.7 ? t/h acquisition time t acq 1.4 ? aperture delay 30 ns aperture jitter <50 ps maximum serial clock frequency f sclk 8 mhz duty cycle 30 70 % analog input unipolar 0 v ref input voltage range (note 4) bipolar -v ref /2 v ref /2 v downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs _______________________________________________________________________________________ 3 electrical characteristics (continued)(v dd = +2.7v to +3.6v, v ref = +2.5v for max1287/max1289, or v dd = +4.75v to +5.25v, v ref = +4.096v for max1286/max1288, 0.1? capacitor at ref, f sclk = 8mhz (50% duty cycle), ain- = gnd for max1288/max1289. t a = t min to t max, unless otherwise noted. typical values at t a = +25?.) parameter symbol conditions min typ max units input leakage current c hannel not sel ected or conver si on stop p ed 0.01 1 a input capacitance 34 pf external reference input input voltage range v ref 1.0 v dd +50mv v v ref = +2.5v at 150ksps 16 30 v ref = +4.096v at 150ksps 26 45 input current i ref acquisition/between conversions 0.01 1 ? digital inputs/outputs (sclk, cnvst, dout) input low voltage v il 0.8 v input high voltage v ih v dd -1 v input leakage current i l ?.01 1.0 ? input capacitance c in 15 pf i sink = 2ma 0.4 v output low voltage v ol i sink = 4ma 0.8 v output high voltage v oh i source = 1.5ma v dd -0.5 v three-state leakage current cnvst = gnd ?.05 10 ? three-state output capacitance c out cnvst = gnd 15 pf power requirements max1286/max1288 4.75 5.0 5.25 positive supply voltage v dd max1287/max1289 2.7 3.0 3.6 v f sample =150ksps 245 350 f sample =100ksps 150 f sample =10ksps 15 v dd = +3v f sample =1ksps 2 f sample =150ksps 320 400 f sample =100ksps 215 f sample =10ksps 22 v dd = +5v f sample =1ksps 2.5 positive supply current i dd shutdown 0.2 5 ? v dd = 5v 5%; full-scale input 0.3 ?.0 positive supply rejection psr v dd = +2.7v to +3.6v; full-scale input 0.4 ?.2 mv downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs 4 _______________________________________________________________________________________ timing characteristics (figures 1, 2, and 5)(v dd = +2.7v to +3.6v, v ref = +2.5v, 0.1? capacitor at ref, or v dd = +4.75v to +5.25v for max1286/max1288, v ref = +4.096v, 0.1? capacitor at ref, f sclk = 8mhz (50% duty cycle); ain- = gnd for max1288/max1289. t a = t min to t max, unless otherwise noted. typical values at t a = +25?.) parameters symbol conditions min typ max units sclk pulse width high t ch 38 ns sclk pulse width low t cl 38 ns sclk fall to dout transition t dot c load = 30pf 60 ns sclk rise to dout disable t dod c load = 30pf 100 500 ns cnvst rise to dout enable t doe c load = 30pf 80 ns cnvst fall to msb valid t conv c load = 30pf 3.7 ? cnvst pulse width t csw 30 ns note 1: unipolar mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range hasbeen calibrated. note 3: offset nulled. note 4: the absolute input voltage range for the analog inputs is from gnd to v dd . ? ? ? ? ? ? ? ? ? cnvst sclk dout t doe high-z high-z t csw t cl t ch t dod t dot dout 6k ? 6k ? c l gnd dout c l gnd v dd a) high -z to v oh , v ol to v oh , and v oh to high -z b) high -z to v ol , v oh to v ol , and v ol to high -z figure 1. detailed serial-interface timing sequence figure 2. load circuits for enable/disable times downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs _______________________________________________________________________________________ 5 -1.0 -0.6-0.8 -0.2-0.4 0.2 0 0.4 0.80.6 1.0 0 1000 1500 2000 500 2500 3000 3500 4000 4500 integral nonlinearity vs. output code max1286-9 toc01 output code inl (lsb) max1287/max1289 -1.0 -0.6-0.8 -0.2-0.4 0.2 0 0.4 0.80.6 1.0 0 1000 1500 2000 500 2500 3000 3500 4000 4500 integral nonlinearity vs. output code max1286-9 toc02 output code inl (lsb) max1286/max1288 -1.0 -0.6-0.8 -0.2-0.4 0.2 0 0.4 0.80.6 1.0 0 1000 1500 2000 500 2500 3000 3500 4000 4500 differential nonlinearity vs. output code max1286-9 toc03 output code dnl (lsb) max1287/max1289 -1.0 -0.6-0.8 -0.2-0.4 0.2 0 0.4 0.80.6 1.0 0 1000 1500 2000 500 2500 3000 3500 4000 4500 differential nonlinearity vs. output code max1286-9 toc04 output code dnl (lsb) max1286/max1288 1000 1 01 0 100 1000 supply current vs. sampling rate 10 100 max1286-9 toc05 sampling rate (ksps) supply current ( a) 0.1 0 1 max1287/max1289 1000 1 supply current vs. sampling rate 10 100 max1286-9 toc06 sampling rate (ksps) supply current ( a) 0.1 01 0 100 1000 0.1 1 max1286/max1288 typical operating characteristics (v dd = +3v, v ref = +2.5v for max1287/max1289. v dd = +5v, v ref = +4.096v for max1286/max1288; 0.1? capacitor at ref, f sclk = 8mhz (50% duty cycle); ain- = gnd for max1288/max1289, t a = +25?, unless otherwise noted.) 0 50 100 200 250150 300 2.7 3.7 4.2 3.2 4.7 5.2 shutdown current vs. supply voltage max1286-9 toc08 v dd (v) shutdown current (na) 180 220200 260240 300 320 340 360280 380 2.7 3.7 4.2 3.2 4.7 5.2 supply current vs. supply voltage max1286-9 toc07 v dd (v) supply current ( a) 180 230 380330 280 430 -40 0 20 -20 40 60 80 supply current vs. temperature max1286-9 toc09 temperature ( c) supply current ( a) max1286 downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = +3v, v ref = +2.5v for max1287/max1284. v dd = +5v, v ref = +4.096v for max1286/max1288; 0.1? capacitor at ref, f sclk = 8mhz (50% duty cycle); ain- = gnd for max1288/max1289, t a = +25?, unless otherwise noted.) 0 100 50 250200 150 300 -40 0 20 -20 40 60 80 shutdown current vs. temperature max1286-9 toc10 temperature ( c) shutdown current (na) -1.00 -0.40-0.60 -0.80 0.00 -0.20 0.800.60 0.40 0.20 1.00 -40 -20 0 20 40 60 80 offset error vs. temperature max1286-9 toc11 temperature ( c) offset error (lsb) -1.0 -0.6-0.8 -0.2-0.4 0.2 0.4 0.6 0.8 0 1.0 2.7 3.7 4.2 3.2 4.7 5.2 offset error vs. supply voltage max1286-9 toc12 v dd (v) offset error (lsb) -40 0 20 -20 40 60 80 gain error vs. temperature max1286-9 toc13 temperature ( c) gain error (lsb) -2.0 -1.2-1.6 -0.4-0.8 0.4 0.8 1.2 1.6 0 2.0 -2.0 -1.2-1.6 -0.4-0.8 0.4 0.8 1.2 1.6 0 2.0 2.7 3.7 4.2 3.2 4.7 5.2 gain error vs. supply voltage max1286-9 toc14 v dd (v) gain error (lsb) -140 -120 -100 -80 -60 -40 -20 0 20 0 15k 30k 45k 60k fft plot (sinad) max1286-9 toc15 frequency (hz) amplitude (db) downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs _______________________________________________________________________________________ 7 detailed description the max1286?ax1289 adcs use a successive-approximation conversion (sar) technique and an on- chip track-and-hold (t/h) structure to convert an analog signal into a 12-bit digital result. the serial interface provides easy interfacing to micro-processors (?s). figure 3 shows the simplified internal structure for the max1286/max1287 (2 channels, sin- gle ended) and the max1288/max1289 (1 channel, true differential). true-differential analog input t/h the equivalent circuit of figure 4 shows themax1286?ax1289s?input architecture, which is com- posed of a t/h, input multiplexer, comparator, and switched-capacitor dac. the t/h enters its tracking mode on the rising edge of cnvst. the positive input capacitor is connected to ain1 or ain2 (max1286/ max1287) or ain+ (max1288/max1289). the negative input capacitor is connected to gnd (max1286/ max1287) or ain- (max1288/max1289). the t/h enters its hold mode on the falling edge of cnvst and the dif- ference between the sampled positive and negative input voltages is converted. the time required for the t/h to acquire an input signal is determined by how quickly its input capacitance is charged. if the input sig- nal? source impedance is high, the acquisition time lengthens, and cnvst must be held high for a longer period of time. the acquisition time, t acq , is the maxi- mum time needed for the signal to be acquired, plus thepower-up time. it is calculated by the following equation: t acq = 9 x (r s + r in ) x 24pf + t pwr 12-bit sar adc control oscillator input shift register t/h ref cnvst sclk dout ain2 (ain-) ain1 (ain+) max1286?ax1289 ( ) are for max1288/max1289 figure 3. simplified functional diagram name pin max1286max1287 max1288max1289 function 1v dd v dd positive supply voltage. +2.7v to +3.6v (max1287/max1289); +4.75v to +5.25v (max1286/max1288). bypass with a 0.1? capacitor to gnd. 2 ain1 ain+ analog input channel 1 (max1286/max1287) or positive analog input (max1288/max1289) 3 ain2 ain- analog input channel 2 (max1286/max1287) or negative analog input (max1288/max1289) 4 gnd gnd ground 5 ref ref external reference voltage input. sets the analog voltage range. bypass with a 0.1?capacitor to gnd. 6 cnvst cnvst conversion start. a rising edge powers up the ic and places it in track mode. at the fallingedge of cnvst, the device enters hold mode and begins conversion. cnvst also selects the input channel (max1286/max1287) or input polarity (max1288/max1289). 7 dout dout serial data output. dout transitions the falling edge of sclk. dout goes low at the start of aconversion and presents the msb at the completion of a conversion. dout goes high impedance once data has been fully clocked out. 8 sclk sclk serial clock input. clocks out data at dout msb first. ep ep exposed pad. connect the exposed pad to ground or leave unconnected. pin description downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs 8 _______________________________________________________________________________________ where r in = 1.5k ? , r s is the source impedance of the input signal, and t pwr = 1? is the power-up time of the device. note: t acq is never less than 1.4? and any source impedance below 300 ? does not significantly affect the adc? ac performance. a high-impedance source canbe accommodated either by lengthening t acq or by placing a 1? capacitor between the positive and neg-ative analog inputs. selecting ain1 or ain2 (max1286/max1287) select one of the max1286/max1287s?two positiveinput channels using the cnvst pin. if ain1 is desired (figure 5a), drive cnvst high to power up the adc and place the t/h in track mode with ain1 connected to the positive input capacitor. hold cnvst high for t acq to fully acquire the signal. drive cnvst low to place the t/h in hold mode. the adc then performs aconversion and shutdown automatically. the msb is available at dout after 3.7?. data can then be clocked out using sclk. clock out all 12 bits of data before driving cnvst high for the next conversion. if all 12 bits of data are not clocked out before cnvst is dri- ven high, ain2 is selected for the next conversion. if ain2 is desired (figure 5b), drive cnvst high for at least 30ns. next, drive it low for at least 30ns, and then high again. this powers up the adc and places the t/h in track mode with ain2 connected to the positive input capacitor. now hold cnvst high for t acq to fully acquire the signal. drive cnvst low to place the t/h inhold mode. the adc then performs a conversion and shutdown automatically. the msb is available at dout after 3.7?. data can then be clocked out using sclk. if all 12 bits of data are not clocked out before cnvstis driven high, ain2 is selected for the next conversion. selecting unipolar or bipolar conversions (max1288/max1289) initiate true-differential conversions with themax1288/max1289s?unipolar and bipolar modes, using the cnvst pin. ain+ and ain- are sampled at the falling edge of cnvst. in unipolar mode, ain+ can exceed ain- by up to v ref . the output format is straight binary. in bipolar mode, either input canexceed the other by up to v ref /2. the output format is two? complement.note: in both modes, ain+ and ain- must not exceed v dd by more than 50mv or be lower than gnd by more than 50mv. if unipolar mode is desired (figure 5a), drive cnvst high to power up the adc and place the t/h in track mode with ain+ and ain- connected to the input capacitors. hold cnvst high for t acq to fully acquire the signal. drive cnvst low to place the t/h in holdmode. the adc then performs a conversion and shut- down automatically. the msb is available at dout after 3.7?. data can then be clocked out using sclk. clock out all 12 bits of data before driving cnvst high for the next conversion. if all 12 bits of data are not clocked out before cnvst is driven high, bipolar mode is selected for the next conversion. if bipolar mode is desired (figure 5b), drive cnvst high for at least 30ns. next, drive it low for at least 30ns and then high again. this places the t/h in track mode with ain+ and ain- connected to the input capacitors. now hold cnvst high for t acq to fully acquire the sig- nal. drive cnvst low to place the t/h in hold mode.the adc then performs a conversion and shutdown automatically. the msb is available at dout after 3.7?. data can then be clocked out using sclk. if all 12 bits of data are not clocked out before cnvst is dri- ven high, bipolar mode is selected for the next conver- sion. input bandwidth the adc? input tracking circuitry has a 1mhz small-signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. rin+ + - hold rin- cin+ ref gnd dac cin- track v dd /2 comparator gnd (ain-) ain2 ain1 (ain+) hold hold ( ) are for max1288/max1289 figure 4. equivalent input circuit downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs _______________________________________________________________________________________ 9 analog input protection internal protection diodes that clamp the analog input tov dd and gnd allow the analog input pins to swing from gnd - 0.3v to v dd + 0.3v without damage. both inputs must not exceed v dd by more than 50mv or be lower than gnd by more than 50mv for accurate conversions.if an off-channel analog input voltage exceeds the supplies, limit the input current to 2ma. internal clock the max1286?ax1289 operate from an internal oscilla-tor, which is accurate within 10% of the 4mhz specified clock rate. this results in a worst-case conversion time of 3.7?. the internal clock releases the system micro- processor from running the sar conversion clock and allows the conversion results to be read back at the processor? convenience, at any clock rate from 0 to 8mhz. cnvst sclk dout t acq t conv sampling instant 4 18 1 2 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb high-z high-z cnvst sclk dout t acq t conv sampling instant 4 18 1 2 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb high-z high-z figure 5b. single conversion ain2 vs. gnd (max1286/max1287), bipolar mode ain+ vs. ain- (max1288/max1289) figure 5a. single conversion ain1 vs. gnd (max1286/max1287), unipolar mode ain+ vs. ain- (max1288/max1289) downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs 10 ______________________________________________________________________________________ output data format figures 5a and 5b illustrate the conversion timing for themax1286?ax1289. the 12-bit conversion result is out- put in msb-first format. data on dout transitions on the falling edge of sclk. all 12 bits must be clocked out before cnvst transitions again. for the max1288/ max1289, data is straight binary for unipolar mode and two? complement for bipolar mode. for the max1286/ max1287, data is always straight binary. transfer function figure 6 shows the unipolar transfer function for themax1286?ax1289. figure 7 shows the bipolar transfer function for the max1288/max1289. code transitions occur halfway between successive-integer lsb values. applications information automatic shutdown mode with cnvst low, the max1286?ax1289 default to anautoshutdown state (< 0.2?) after power-up and between conversions. after detecting a rising edge on cnvst, the part powers up, sets dout low, and enters track mode. after detecting a falling edge on cnvst, the device enters hold mode and begins the conversion. a maximum of 3.7? later, the device completes conver- sion, enters shutdown, and msb is available at dout. external reference an external reference is required for the max1286max1289. use a 0.1? bypass capacitor for best per- formance. the reference input structure allows a volt- age range of +1v to v dd + 50mv. connection to standard interfaces the max1286?ax1289 feature a serial interface that isfully compatible with spi, qspi, and microwire. if a serial interface is available, establish the cpu? serial interface as a master, so that the cpu generates the seri- al clock for the adcs. select a clock frequency up to 8mhz. how to perform a conversion 1) use a general-purpose i/o line on the cpu to hold cnvst low between conversions. 2) drive cnvst high to acquire ain1(max1286/ max1287) or unipolar mode (max1288/max1289).to acquire ain2 (max1286/max1287) or bipolar mode (max1288/max1289), drive cnvst low and high again. 3) hold cnvst high for 1.4?. 4) drive cnvst low and wait approximately 3.7? for conversion to complete. after 3.7?, the msb isavailable at dout. output code full-scale transition 11 . . . 11111 . . . 110 11 . . . 101 00 . . . 01100 . . . 010 00 . . . 001 00 . . . 000 123 0 fs fs - 3/2 lsb fs = v ref zs = gnd input voltage (lsb) max1286 max1289 1 lsb = v ref 4096 figure 6. unipolar transfer function 011 . . . 111011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs 0 input voltage (lsb) output code zs = 0 +fs - 1 lsb *v com v ref / 2 *v in = (ain+) - (ain-) fs = v ref 2 -fs = -v ref 2 max1288/max1289 1 lsb = v ref 4096 figure 7. bipolar transfer function downloaded from: http:///
5) activate sclk for a minimum of 12 rising clock edges. dout transitions on sclk? falling edgeand is available in msb-first format. observe the sclk to dout valid timing characteristic. clock data into the ? on sclk? rising edge. spi and microwire interface when using an spi (figure 8a) or microwire inter-face (figures 8a and 8b), set cpol = cpha = 0. two 8-bit readings are necessary to obtain the entire 12-bit result from the adc. dout data transitions on the seri- al clock? falling edge and is clocked into the ? on sclk? rising edge. the first 8-bit data stream contains the first 8-bits of dout starting with the msb. the sec- ond 8-bit data stream contains the remaining four result bits. dout then goes high impedance. qspi interface using the high-speed qspi interface (figure 9a) withcpol = 0 and cpha = 0, the max1286?ax1289 support a maximum f sclk of 8mhz. one 12- to 16-bit reading is necessary to obtain the entire 12-bit resultfrom the adc. dout data transitions on the serial clock? falling edge and is clocked into the ? on sclk? rising edge. the first 12 bits are the data.dout then goes high impedance (figure 9b). pic16 and ssp module and pic17 interface the max1286?ax1289 are compatible with apic16/pic17 ?, using the synchronous serial port (ssp) module to establish spi communication, connect the controller as shown in figure 10a and configure the pic16/pic17 as system master. this is done by initializing its syn- chronous serial port control register (sspcon) and synchronous serial port status register (sspstat) to the bit patterns shown in tables 1 and 2. in spi mode, the pic16/pic17 ?s allow 8 bits of data to be synchronously transmitted and received simulta- neously. two consecutive 8-bit readings (figure 10b) are necessary to obtain the entire 12-bit result from the adc. dout data transitions on the serial clock? falling edge and is clocked into the ? on sclk? rising edge. the first 8-bit data stream contains the first 8 data bits starting with the msb. the second data stream con- tains the remaining bits, d3 through d0. max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs ______________________________________________________________________________________ 11 figure 8a. spi connections figure 8b. microwire connections cnvst sclk dout i/o sck miso v dd ss spi max1286 max1289 max1286 max1289 cnvstsclk dout i/o sk si microwire table 1. detailed sspcon register content control bit max1286?ax1289 settings synchronous serial port control register (sspcon) wcol bit 7 x write collision detection bit sspov bit 6 x receive overflow detect bit sspen bit 5 1 synchronous serial port enable bit:0: disables serial port and configures these pins as i/o port pins. 1: e nab l es ser i al p or t and confi g ur es s c k, s d o, and s c i p i ns as ser i al p or t p i ns. ckp bit 4 0 clock polarity select bit. ckp = 0 for spi master mode selection. sspm3 bit 3 0 sspm2 bit 2 0 sspm1 bit 1 0 sspm0 bit 0 1 synchronous serial port mode select bit. sets spi master mode and selectsf clk = f osc / 16. downloaded from: http:///
max1286?ax1289 layout, grounding, and bypassing for best performance, use printed circuit (pc) boards.wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the adc package. use separate analog and digital pc board ground sections with only one starpoint (figure 11), connecting the two groundsystems (analog and digital). for lowest-noise opera- tion, ensure the ground return to the star ground? power supply is low impedance and as short as possi- ble. route digital signals far away from sensitive analog and reference inputs. high-frequency noise in the power supply (v dd ) may degrade the performance of the adc? fast comparator.bypass v dd to the star ground with a 0.1? capacitor, located as close as possible to the max1286?ax1289spower-supply pin. minimize capacitor lead length for best supply-noise rejection. add an attenuation resistor (5 ? ) if the power supply is extremely noisy. 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs 12 ______________________________________________________________________________________ cnvstsclk dout cs sck miso v dd ss qspi max1286 max1289 figure 9a. qspi connections table 2. detailed sspstat register content control bit max1286?ax1289 settings synchronous serial status register (sspstat) smp bit 7 0 spi data input sample phase. input data is sampled at the middle of the dataoutput time. cke bit 6 1 spi clock edge select bit. data is transmitted on the rising edge of the serialclock. d/a bit 5 x data address bit p bit 4 x stop bit s bit 3 x start bit r/w bit 2 x read/write bit information ua bit 1 x update address bf bit 0 x buffer full status bit figure 8c. spi/microwire interface timing sequence (cpol = cpha = 0) cnvst 1st byte read sclk dout 2nd byte read sampling instant 4 18 12 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb high-z 16 downloaded from: http:///
definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the valueson an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the sta- tic linearity parameters for the max1286?ax1289 are measured using the end-point method. differential nonlinearity differential nonlinearity (dnl) is the difference betweenan actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs ______________________________________________________________________________________ 13 cnvst sclk dout sampling instant 4 18 12 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb high-z 16 figure 9b. qspi interface timing sequence (cpol = cpha = 0) scksdi gnd gnd i/o sclk dout cnvst v dd v dd max1286 max1289 pic16/pic17 figure 10a. spi interface connection for a pic16/pic17 controller cnvst 1st byte read sclk dout 2nd byte read sampling instant 4 18 12 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb high-z 16 figure 10b. spi interface timing with pic16/pic17 in master mode (cke = 1, ckp = 0, smp = 0, sspm3 - sspm0 = 0001) downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs 14 ______________________________________________________________________________________ aperture definitions aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay (t ad ) is the time between the rising edge of the sampling clockand the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital sam-ples, signal-to-noise ratio (snr) is the ratio of full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to- digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr = (6.02 ? n + 1.76)db in reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of thefundamental input frequency? rms amplitude to rms equivalent of all other adc output signals. sinad (db) = 20 ? log (signal rms / noise rms ) effective number of bits effective number of bits (enob) indicates the globalaccuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rmssum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order har- monics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rmsamplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component. chip information transistor count: 6922process: bicmos thd vvvv v = +++ ? ? ? ? ? ? ? ? 20 2345 2222 1 log v logic = +5v or +3v gnd supplies dgnd +5v or +3v gnd 0.1 f v dd digital circuitry max1286 max1289 r* = 5 ? *optional +5v or +3v figure 11. power-supply and grounding connections package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw-ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 sot23 k8f-4 21-0078 90-0176 8 tdfn t833+2 21-0137 90-0059 downloaded from: http:///
max1286?ax1289 150ksps, 12-bit, 2-channel single-ended, and 1-channel true-differential adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision revision description pages changed 3 8/10 added exposed pad to tdfn package and soldering temperature 1, 2 downloaded from: http:///

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